1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including highly conductive metals, such as copper, embedded into a dielectric material, wherein the copper-based metal material receives a nitrogen-containing copper silicide (CuSiN) surface portion for enhancing electromigration performance of the metal.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per chip.
In integrated circuits having minimum dimensions of approximately 0.35 μm and less, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements has now reached 50 nm and less, the signal propagation delay is no longer limited by the field effect transistors but is limited, owing to the increased circuit density, by the interconnect lines, since the line-to-line capacitance (C) is increased and also the resistance (R) of the lines is increased due to their reduced cross-sectional area. The parasitic RC time constants therefore require the introduction of a new type of material for forming the metallization layer.
Traditionally, metallization layers, i.e., the wiring layers including metal lines and vias for providing the electrical connection of the circuit elements according to a specified circuit layout, are formed by a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities than may be necessary in integrated circuits having extremely scaled feature sizes, aluminum is being replaced by copper, which has a significantly lower electrical resistance and a higher resistivity against electromigration. For highly sophisticated applications, in addition to using copper and/or copper alloys, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>5) may be replaced by so-called low-k dielectric materials. However, the transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a copper-based metallization layer possibly in combination with a low-k dielectric material is associated with a plurality of issues to be dealt with.
For example, copper may not be deposited in relatively high amounts in an efficient manner by well-established deposition methods, such as chemical and physical vapor deposition. Moreover, copper may not be efficiently patterned by well-established anisotropic etch processes. Therefore, the so-called damascene or inlaid technique is frequently employed in forming metallization layers including copper lines and vias. Typically, in the damascene technique, the dielectric layer is deposited and then patterned for receiving trenches and via openings that are subsequently filled with copper by plating methods, such as electroplating or electroless plating. Moreover, since copper readily diffuses in a plurality of dielectrics, such as silicon dioxide and in many low-k dielectrics, the formation of a diffusion barrier layer at interfaces with the neighboring dielectric material may be required. Moreover, the diffusion of moisture and oxygen into the copper-based metal has to be suppressed as copper readily reacts to form oxidized portions, thereby possibly deteriorating the characteristics of the copper-based metal line with respect to adhesion, conductivity and the resistance against electromigration. In order to not unduly reduce the overall conductivity of the metal region, conductive barrier materials are typically used for covering inner sidewall areas of trenches, while dielectric barrier materials are used as capping layers, which may also act as an efficient etch stop material when contacting the metal region by a via from a metal region of a next higher metallization level. For instance, silicon nitride is known as an effective copper diffusion barrier and may be used, for instance, as a capping layer. In other cases, when the moderately high permittivity of silicon nitride is considered inappropriate, nitrogen-enriched silicon carbide (SiCN) is frequently used as a copper diffusion barrier. Despite the diffusion hindering effect of the silicon nitride capping layers and silicon carbide based capping layers, it turns out, however, that copper's resistance against electric current induced material transport (electromigration) or other stress induced material transport effects strongly depends on the characteristics of an interface between the copper-based metal and the adjacent capping layer. Therefore, in sophisticated integrated circuits featuring high current densities, it is generally important to design the interface between the copper-based metal and the capping layer such that a desired high adhesion and thus high performance with respect to electromigration or stress induced mass transport is achieved. In this respect, nitrogen-containing copper silicide (CuSiN) has been identified as an efficient alloy, which may result in a highly stable interface, thereby endowing the corresponding metal region with increased resistance and thus reliability with respect to electromigration and other stress induced mass transport effects.
Hence, in some conventional approaches, the copper surface is exposed to a reactive gas ambient, such as a plasma assisted gas ambient, which may contain silane (SiH4) as a silicon-containing precursor and a nitrogen-containing gas, thereby creating the copper silicide with a specific fraction of nitrogen. Usually, the process for forming the CuSiN material at the exposed copper interface is performed immediately prior to the plasma enhanced chemical vapor deposition (PECVD) of the barrier material, such as silicon nitride, nitrogen-enriched silicon carbide or combinations thereof, wherein respective cleaning processes, such as plasma enhanced processes and the like, may be performed in order to prepare the copper surface for the subsequent formation of the CuSiN alloy and the deposition of the barrier/etch stop material. Thus, a plurality of complex processes may be involved that may interact with the copper surface and therefore result in complex surface conditions, which may therefore require precisely controlled process conditions during the formation of the CuSiN material. It turns out that even minute variations of process conditions may result in significant differences of the composition of the resulting CuSiN material, thereby even deteriorating the characteristics of the copper near the surface. Thus, although CuSiN is a promising candidate for enhancing the performance of copper-based metallization structures, the process is difficult to control, since, for instance, a slight imbalance of the precursor materials may result in non-predictable performance characteristics of the metal line.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.